Closing the power gap between ASIC & custom / Chinnery, David (2007)

Public ISBD Titre : Closing the power gap between ASIC & custom Type de document : document électronique Auteurs : Chinnery, David, Auteur ; Keutzer, Kurt William, Auteur Editeur : Berlin ; London ; Cham : Springer Année de publication : 2007 ISBN/ISSN/EAN : 978-0-387-68953-1 Langues : Anglais (eng) Mots-clés : Circuits intégrés Circuits imprimés -- Conception et construction -- Informatique Index. décimale : 621.381 Résumé : This document carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times. Closing the power gap between ASIC & custom [document électronique] / Chinnery, David, Auteur ; Keutzer, Kurt William, Auteur . - Berlin ; London ; Cham : Springer, 2007. ISBN : 978-0-387-68953-1 Langues : Anglais (eng) Mots-clés : Circuits intégrés Circuits imprimés -- Conception et construction -- Informatique Index. décimale : 621.381 Résumé : This document carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times.

Réservation

Réserver ce document

Exemplaires (2)

Code-barres	Cote	Support	Localisation	Section	Disponibilité	Etat_Exemplaire
E00279	621.381 CHI	Ressources électroniques	Bibliothèque Centrale	Electronique	Disponible
E00280	621.381 CHI	Ressources électroniques	Bibliothèque Centrale	Electronique	Disponible

Compiling esterel / Potop-Butucaru, Dumitru (2007)

Public ISBD Titre : Compiling esterel Type de document : document électronique Auteurs : Potop-Butucaru, Dumitru, Auteur ; Berry, Gérard, Auteur Editeur : Berlin ; London ; Cham : Springer Année de publication : 2007 Collection : Engineering ISBN/ISSN/EAN : 978-0-387-70628-3 Langues : Anglais (eng) Mots-clés : Electronics Engineering Design Engineering Index. décimale : 621.381 Note de contenu : Esterel is based on the simple idea of providing a software language that has a synchronous model of time. That is, the execution of the program is divided into discrete instants, and statements are either guaranteed to execute in a single instant, or take multiple instants as requested by the programmer. Suitable for programming safety-critical real-time systems, Esterel and its model of computation have found use in industrial applications such as avionics, integrated circuit design, and other safety-critical environments. While Compiling Esterel does not assume prior knowledge of the Esterel language, readers will appreciate having prior knowledge of programming language semantics and compiler technology, along with some familiarity with synchronous digital hardware design. Researchers as well as advanced developers will find Compiling Esterel essential for understanding Esterel at all levels. Compiling esterel [document électronique] / Potop-Butucaru, Dumitru, Auteur ; Berry, Gérard, Auteur . - Berlin ; London ; Cham : Springer, 2007. - (Engineering) . ISBN : 978-0-387-70628-3 Langues : Anglais (eng) Mots-clés : Electronics Engineering Design Engineering Index. décimale : 621.381 Note de contenu : Esterel is based on the simple idea of providing a software language that has a synchronous model of time. That is, the execution of the program is divided into discrete instants, and statements are either guaranteed to execute in a single instant, or take multiple instants as requested by the programmer. Suitable for programming safety-critical real-time systems, Esterel and its model of computation have found use in industrial applications such as avionics, integrated circuit design, and other safety-critical environments. While Compiling Esterel does not assume prior knowledge of the Esterel language, readers will appreciate having prior knowledge of programming language semantics and compiler technology, along with some familiarity with synchronous digital hardware design. Researchers as well as advanced developers will find Compiling Esterel essential for understanding Esterel at all levels.

Réservation

Réserver ce document

Exemplaires (2)

Code-barres	Cote	Support	Localisation	Section	Disponibilité	Etat_Exemplaire
E00269	621.381 POT	Ressources électroniques	Bibliothèque Centrale	Electronique	Disponible
E00270	621.381 POT	Ressources électroniques	Bibliothèque Centrale	Electronique	Disponible