Logic synthesis and optimization / International symposium on logic synthesis and microprocessor architecture (juillet 1992; Iizuka, Japan) (1993)

Public ISBD Titre : Logic synthesis and optimization Type de document : texte imprimé Auteurs : Tsutomu Sasao, Éditeur scientifique Congrès : International symposium on logic synthesis and microprocessor architecture (juillet 1992; Iizuka, Japan), Auteur Editeur : Boston : Kluwer academic publishers Année de publication : 1993 Collection : The kluwer international series in engineering and computer science Sous-collection : VLSI, computer architecture and digital signal processing num. 212 Importance : XV-375 p. Présentation : ill. Format : 24 cm ISBN/ISSN/EAN : 978-0-7923-9308-5 Note générale : Bibliogr. Index Langues : Anglais (eng) Mots-clés : Logic circuits -- Design and construction -- Data processing Logic design -- Data processing Computer-aided design Circuits logiques -- Conception et construction Conception assistée par ordinateur Index. décimale : 62-52 Machine et processus conduits ou contrôlés automatiquement Résumé : Focuses on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array design, EXOR logic synthesis and technology mapping. Note de contenu : Contents: 1. A New Exact Minimizer for Two-Level Logic Synthesis. 2. A New Graph Based Prime Computation Technique. 3. Logic Synthesizers, the Transduction Method and Its Extension, Sylon. 4. Network Optimization Using Don't-Cares and Boolean Relations. 5. Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning. 6. A Partitioning Method for Area Optimization by Tree Analysis. 7. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams. 8. Delay Models and Exact Timing Analysis. 9. Challenges to Dependable Asynchronous Processor Design. Logic synthesis and optimization [texte imprimé] / Tsutomu Sasao, Éditeur scientifique / International symposium on logic synthesis and microprocessor architecture (juillet 1992; Iizuka, Japan), Auteur . - Boston : Kluwer academic publishers, 1993 . - XV-375 p. : ill. ; 24 cm. - (The kluwer international series in engineering and computer science. VLSI, computer architecture and digital signal processing; 212) . ISBN : 978-0-7923-9308-5 Bibliogr. Index Langues : Anglais (eng) Mots-clés : Logic circuits -- Design and construction -- Data processing Logic design -- Data processing Computer-aided design Circuits logiques -- Conception et construction Conception assistée par ordinateur Index. décimale : 62-52 Machine et processus conduits ou contrôlés automatiquement Résumé : Focuses on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array design, EXOR logic synthesis and technology mapping. Note de contenu : Contents: 1. A New Exact Minimizer for Two-Level Logic Synthesis. 2. A New Graph Based Prime Computation Technique. 3. Logic Synthesizers, the Transduction Method and Its Extension, Sylon. 4. Network Optimization Using Don't-Cares and Boolean Relations. 5. Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning. 6. A Partitioning Method for Area Optimization by Tree Analysis. 7. A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams. 8. Delay Models and Exact Timing Analysis. 9. Challenges to Dependable Asynchronous Processor Design.

Réservation

Réserver ce document

Exemplaires (1)

Code-barres	Cote	Support	Localisation	Section	Disponibilité	Etat_Exemplaire
041532	62-52 INT	Papier	Bibliothèque Centrale	Automatique	Disponible	En bon état