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Closing the power gap between ASIC & custom / Chinnery, David

Public ISBD Titre : Closing the power gap between ASIC & custom Type de document : document électronique Auteurs : Chinnery, David, Auteur ; Keutzer, Kurt William, Auteur Editeur : Berlin : Springer Année de publication : 2007 ISBN/ISSN/EAN : 978-0-387-68953-1 Langues : Anglais (eng) Mots-clés : Circuits  intégrés  Circuits  imprimés  --  Conception  et  construction  --  Informatique Index. décimale : 621.381 Résumé : This document carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times. Closing the power gap between ASIC & custom [document électronique] / Chinnery, David, Auteur ; Keutzer, Kurt William, Auteur . - Berlin : Springer, 2007. ISBN : 978-0-387-68953-1 Langues : Anglais (eng) Mots-clés : Circuits  intégrés  Circuits  imprimés  --  Conception  et  construction  --  Informatique Index. décimale : 621.381 Résumé : This document carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times.

Exemplaires

Code-barres	Cote	Support	Localisation	Section	Disponibilité	Etat_Exemplaire
E00279	621.381 CHI	Ressources électroniques	Bibliothèque Centrale	Electronique	Disponible
E00280	621.381 CHI	Ressources électroniques	Bibliothèque Centrale	Electronique	Disponible