| Titre : | Unified methods for VLSI simulation and test generation |
| Auteurs : | Ting-Kwang Cheng, Auteur ; Vishwani D. Agrawal, Auteur |
| Type de document : | texte imprimé |
| Editeur : | Boston : Kluwer academic publishers, 1989 |
| Autre Editeur : | Norwell [États-Unis] : AT&T bell laboratories |
| Collection : | The kluwer international series in engineering and computer science |
| Sous-collection : | VLSI, computer architecture and digital signal processing, num. 73 |
| ISBN/ISSN/EAN : | 978-0-7923-9025-1 |
| Format : | XII-148 p. / ill. / 24 cm |
| Note générale : | Bibliogr. p. [113]-143. Index |
| Langues : | Anglais |
| Index. décimale : | 621.382 (Dispositifs électroniques utilisant les effets des corps solides. Dispositifs semi-conducteurs ) |
| Tags : | Integrated circuits -- Very large scale integration -- Computer-aided design Integrated circuits -- Very large scale integration -- Testing Integrated circuits -- Very large scale integration -- Computer simulation |
| Résumé : | In ensuring the quality of a VLSI device, the verification of design and testing of the product are two of the most important steps. Unified methods for VLSI simulation and test generation combines the two steps in one CAD tool. Building on the power of event-driven logic simulation and concurent fault simulation, the authors develop a directed-search methodology for the generation of production tests. |
| Note de contenu : |
Contents:
* Logic simulation and fault analysis. * The generation approaches. * Simulation-based directed-search approach. * Threshold-value simulation. * Test generation using threshold-value simulation. * Test generation in concurrent fault simulator. |
Exemplaires (2)
| Cote | Support | Localisation | Section | Disponibilité | Etat_Exemplaire |
|---|---|---|---|---|---|
| 621.382 CHE | Papier | Bibliothèque Centrale | Electronique | Disponible | |
| 621.382 CHE | Papier | Bibliothèque Centrale | Electronique | Disponible | En bon état |
